module voter_7bit(
	input [6:0] Vote,
	output reg Pass
);

	reg[2:0] counter;
	integer i;
	
	always @(Vote) begin
	
		counter = 0;
		for(i = 0; i <= 6; i = i+1) begin
			if(Vote[i]) begin
				counter = counter + 1;
			end
		end
		
		if(counter[2]) begin
			Pass = 1'b1;
		end
		else begin
			Pass = 1'b0;
		end
	
	end

endmodule
